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2. Which unit in the IA-32 instruction cycle receives machine instructions from the BIU and inserts them into the instruction queue?
code prefetch unit
4. Which component of an operating system is responsible for switching control between tasks
5. Identify three types of segments that would be referenced by segment registers.
code, data, stack
8. In the Flat segmentation model, which table holds the addresses of segments?
global descriptor table (GDT)
9. List at least five types of ports found on a typical PC motherboard
parallel, serial, USB, video, keyboard, joystick, mouse
12. Why are serial ports typically slower than parallel ports?
serial transfers 1 bit at a time, parrallel transfers multiple bits simultaneously
17. What special feature makes VRAM better-suited to use with a video adapter than DRAM?
VRAM is dual-ported
20. If you wanted to turn a device on and off using computer software, which type of port interface would be best?
23. How is Virtual-8086 mode similar to Real-address mode?
simulates 8086-based computer running in Real-address mode
24. High-speed memory that reduces the frequency of access by the CPU to conventional memory is called
25. Why are device drivers needed, given that BIOS programs can do the same task?
device drivers allow for the introduction of new devices
26. An interpreter program inside the CPU is written in a language called a(n) _______.
27. If you wanted to find out whether an integer contained an even number of 1 bits, which status flag would be useful?
28. In regard to multitasking, a task's state consists of which three elements?
register contents, task variables, program counter
31. If a clock oscillates 10 billion times per second, what is the duration of a single clock cycle?
1.0 x 10-10 seconds
33. The control unit (CU) coordinates the sequencing of steps involved in executing machine instructions.
45. In the multi-segment model (Protected mode), each program is given its own local descriptor table.
47. In Protected mode, the total memory used by all running programs can never be larger than the computer's physical memory.
49. What is the name of the time delay in a CPU caused by differences between the speed of the CPU, the system bus, and memory circuits?
50. List the three primary steps of the instruction execution cycle, in sequential order:
fetch, decode, execute
51. Which stage in the IA-32 instruction cycle is responsible for translating logical addresses to linear addresses and performing protection checks?
52. What are the six stages, or units involved in executing a single IA-32 instruction?
bus interface, code prefetch, instruction decode, execution, segment, paging
54. In a 4-stage non-pipelined processor, how many clock cycles are required to execute 3 instructions? (Assume that each stage executes in a single clock cycle.)
55. In a 4-stage single-pipelined processor, how many clock cycles are required to execute 3 instructions? (Assume that each stage executes in a single clock cycle.)
56. In a 6-stage dual-pipelined processor, how many clock cycles are required to execute 5 instructions? (Assume that stage 4 requires two clock cycles, and that stage 4 has two pipelines
57. Which of the following correctly describes the sequence of reading from memory during a single clock cycle?
Address placed on bus; Read line set low; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data.
61. When the CPU tries to execute part of a program that has been swapped out to disk, it executes a
62. What is the term used for executing horizontal and vertical retrace on a CRT video monitor?
64. Which of the following describe(s) RISC processors?
short, simple instructions, executed quickly
instructions are executed directly by hardware
65. Which of the following is(are) advantages of USB ports over parallel ports?
query devices to get name and type of device
permits a hub to be connected
can suspend power to devices
66. Which type of output is the most general and portable to different computer systems?
. using C++ stream output statements
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