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Terms in this set (32)
Does the following change to a computer system increase throughput, decrease response time, or both?
Replacing the processor in a computer with a faster version. (p. 28)
Both.
Does replacing the processor in a computer with a faster version increase throughput, decrease response time, or both?
Adding additional processors to a system that uses multiple processors for separate tasks -- for example, searching the web. (p. 28)
Throughput only.
If computer A runs a program in 10 seconds and computer B runs the same program in 15 seconds, how much faster is A than B?
A is 1.5 times faster than B.
Our favorite program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help a computer designer build a computer, B, which will run this program in 6 seconds. The designer has determined that a substantial increase inthe clock rate is possible, but this increase will affect the rest of the CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this program. What clock rate should we tell the designer to target? (p. 32)
4 GHz clock rate, or twice the clock rate of A.
Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program, and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much?
Computer A is 1.2 times as fast as computer B for this program.
A compiler designer is trying to decide between two code sequences for a particular computer. The hardware designers have supplied the following facts:
CPI for each instruction class:
A = 1;
B = 2;
C = 3;
Instruction counts for each instruction class:
Sequence 1:
A = 2; B = 1; C = 2;
Sequence 2:
A = 4; B = 1; C = 1
Which code sequence executes the most instructions? Which will be faster? What is the CPI for each sequence? (p. 35)
Sequence 1 executes fewer instructions, but sequence 2 is faster with less clock cycles. The CPI for Sequence 1 is 2.0. The CPI for Sequence 2 is 1.5.
Suppose we developed a new, simpler processor that had 85% of the capacitive load of the more complex older processor. Further, assume that it has adjustable voltage so that it can reduce voltage 15% compared to processor B, which results in a 15% shrink in frequency. What is the impact on dynamic power? (p. 40)
0.52: 1.00, so the new processor uses about half the power of the old processor.
A somewhat complex statement contains the five variables f, g, h, i, and j:
f = (g + h) - (i + j);
What might a C compiler produce?
add $t0, g, h
add $t1, i, j
sub f, $t0, $t1
It is the compiler's job to associate program variables with registers. Take, for instance:
f = (g + h) - (i + j);
The variables f, g, h, i, and j are assigned to the registers $s0, $s1, $s2, $s3, and $s4, respectively. What is the compiled MIPS code?
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Let's assume that A is an array of 100 words and that the compiler has associated the variables g and h with the registers $s1 and $s2. Let's also assume that the starting address, or base address, of the array A is in $s3. Compile this C assignment statement:
g = h+A[8];
lw $t0, 8($s3)
add $s1, $t0, $s2
Assume variable h is associated with register $s2 and the base address of the array A is in $s3. What is the MIPS assembly code for the C assignment statement below?
A[12] = h + A[8]
lw $t0, 8($s3)
add $t0, $t0, $s2
sw $t0, 12(s3)
What is the decimal value of this 32-bit two's complement number?
1111 1111 1111 1111 1111 1111 111 1100_two
-4
(add one & negate it)
Convert this 16-bit binary version of 2_ten to 32-bit binary numbers.
0000 0000 0000 0010
0000 0000 0000 0000 0000 0000 0000 0010
What is the 16-bit binary version of -2_ten?
1111 1111 1111 1110
Covert this 16-bit binary representation of -2_ten to 32-bit binary numbers.
1111 1111 1111 1110
1111 1111 1111 1111 1111 1111 1111 1110
What is the decimal & binary representations of:
add $t0, $s1, $s2 (95)
decimal: 0 17 18 8 0 32
binary: 000000 10001 10010 01000 00000 100000
Convert the following hexadecimal number into binary:
eca8 6420
1110 1100 1010 1000 0110 0100 0010 0000
Convert the following binary number to hexadecimal?
0001 0011 0101 0111 1001 1011 1101 1111
1357 9bdf
Which of the following MIPS functions are R-type?
- add,
- sub,
- addi,
- lw,
- sw
(p. 100)
add, sub
Which of the following MIPS functions are I-type?
- add,
- sub,
- addi,
- lw,
- sw
(p. 100)
addi, lw, sw
If the variables f through j correspond to the five registers $s0 through $s4, what is the compiled MIPS code for this C if statement?
if (i == j)
f = g + h;
else
f = g - h
f = $s0
g = $s1
h = $s2
i = $s3
j = $s4
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else :
sub $s0, $s1, $s2
Exit:
Assume that i and k correspond to registers $s3 and $s5 and the base of the array save is in $s6. What is the MIPS assembly code corresponding to this C segment?
while(save[i] == k)
i +=1;
Loop:
sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $s5, $t0, Exit
addi $s3, $s3, 1
j Loop;
Exit:
Suppose register $s0 has the binary number
1111 1111 1111 1111 1111 1111 1111 1111_two
and that register $s1 has the binary number
0000 0000 0000 0000 0000 0000 0000 0001_two.
What are the values of registers $t0 and $t1 after these two instructions?
slt $t0, $s0, $s1
sltu $t1, $s0, $s1
(p. 110)
$t0 = 1, as -1 < 1
$t1 = 0, 4,294, 967,295 > 1
Turn the following C code into MIPS. Leave all register values the same as they were before you used them.
int leaf_example(int g, int h, int i, int j) {
return (g + h) - (i + j);
}
leaf_example:
# Save the registers to the stack
addi $sp, $sp, -8
sw $t1, 4($sp)
sw $t0, 0($sp)
add $t0, $a0, $a1
add $t1, $a1, $a2
sub $v0, $t0, $t1
lw $t0, 0($sp)
lw $t1, 4($sp)
addi $sp, $sp, 8
jr $ra
int fact (int n) {
if (n < 1)
return 1;
else
return n* fact(n-1)
}
What is this in MIPS code?
fact:
addi $sp, $sp, -8
sw $ra, 0($sp)
sw $a0, 4($sp)
slti $t0, $a0, 1
beq $t0, $zero, L1
addi $v0, $zero, 1
addi $sp, $sp, 8
jr $ra
L1:
addi $a0, $a0, -1
jal fact
lw $a0, 0($sp)
lw $ra, 4($sp)
addi $s0, $sp, 8
mul $v0, $a0, $v0
jr $ra
What is the MIPS assembly code to load this 32-bit constant into register $s0?
0000 0000 0011 1101 0000 1001 0000 0000
lui $s0, 61
ori $s0, $s0, 2304
What is the assembly language statement corresponding to the following instruction?
00af 8020 - hex
add $s0, $a1, $t7
Using 4-bit numbers to save space, multiple 2_ten * 3_tex, or 0010_two x 0011_two
0000 0110
Using a 4-bit version of the algorithm to save pages, divide 7_ten by 2_ten, or 0000 0111 by 0010.
0000 0011 with a remainder of 0001
Compare the average time between instructions of a single-cycle implementation, in which all instructions take one clock cycle, to a pipelined implementation. The operation times for the major functional units in this example are 200 ps for memory access, 200 ps for ALU operation, and 100 ps for register file read or write. In the single-cycle model, every instruction takes exactly one clock cycle, so the clock cycle must be stretched to accommodate the slowest instruction.
What is the time taken for each of these instruction classes?
- load word
- store word
- R-format
- Branch
LW: 800 ps
SW: 700 ps
R-Format: 600 ps
Branch: 500 ps
Consider the following code segment in C:
a = b + e;
c = b + f;
Here is the MIPS code:
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1, $t4
sw $t5, 16($to)
Rewrite this to avoid any hazards & pipeline stalls.
lw $t1, 0($t0)
lw $t2, 4($t0)
lw $t4, 8($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
add $t5, $t1, $t4
sw $t5, 16($to)
Estimate the impact on the clock cycles per instruction (CPI) of stalling on branches. Assume all other instructions have a CPI of 1. Assume 17% of instructions executed are branches.
It would be a slowdown of 1.17:the ideal case (no branches)
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