Fetch Decode Execute Cycle
Terms in this set (11)
Memory Address Register
Holds a copy of the address of the next instruction. Sends it on the address bus to RAM.
Program Counter (PC)
Holds the address of the next instruction to be fetched from memory.
Memory Data Register
Temporarily holds the data/ instruction from the data bus that has been fetched from RAM.
Current Instruction Register
Holds the instruction in use, whilst it is decoded.
Manages the FDE cycle and all the parts of the processor. Sends control signals to synchronise them all together.
Does the decoding and tells the ALU what to do, updates the PC and/ or the MAR.
RAM. Contains data, parts of the operating system and parts of the programs that are currently in use.
One way bus that carries the address locations of data/ instructions to RAM.
Carries data and instructions around the processor and to and from RAM.
Carries control signals e.g. clock signals, input/ output requests, around the processor and to other devices.
Arithmetic Logic Unit
The circuits that do the math and logic operations inside the processor. The "gateway" all inputs and outputs pass through (according to OCR)
A register inside the processor that is used as a temporary working area for the ALU.
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Fetch - Decode - Execute Cycle