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VLSI Midterm 2
Terms in this set (16)
What is an IC?
A device having multiple electronic components and their interconnects manufactured on a single substrate.
VLSI Design Styles
Full Custom- Every gate is special. Basically not done anymore.
ASIC- Gates all come from library, but connections all unique.
SOC- Chip consists of blocks that were all created before. Silicon "printed circuit board".
Real VLSI chips often use a little bit of all three styles in them.
-Might be on custom analog block, ASIC gates, and a couple of larger "IP" blocks.
Gives the designer the most freedom.
-Lots of rope
-Can be clever
-Can hang yourselves too
For a specific function:
-Can achieve best performance (speed, power, area, etc).
-Most work/time per function.
-Optimizations are at a low level.
-Circuit better be important
think assembler, only worse.
ASIC (Application Specific Integrated Circuits)
-Separate teams to design and verify.
-Physical design is (semi-) automated.
-Loops to get device operating frequency correct can be troubling.
SOC (System on a Chip)
-Can buy "intellectual property" (IP) from various vendors.
-"Soft IP": RTL or gate level description.
-Synthesize and place route for your process (Ethernet, MAC, USB).
-"Hard IP": Polygon level description.
-Just hook it up (XAUI Backplane driver, embedded DRAM)
Also: standard cell libraries for ASIC flow.
Structured Design Principles: Important metrics for measuring the quality of design
-Generation of good test vectors.
-Availability of reliable test fixture at speed.
-Design of testable chip.
Yield and Manufacturability:
-Functional yield: tested for functionality at lower than required speed.
-Parametric yield: tested for functionality at required speed
-Electrostatic discharge (ESD)
-Power and group bouncing
-On-chip noise and cross-talk
MOSFET I-V Characteristics:
-We have seen how the Gate-to-Source voltage (VGS) induces a channel between the Source and Drain for current to flow through.
-This current is denoted IDS.
-Remember that this current doesn't flow unless a potential exists between VD and VS.
-The voltage that controls the current flow is denoted as VDS.
-Once again, we start by applying a small voltage and watching how IDS responds.
-Notice that now we actually have two control variables that effect the current flow, VGS and VDS.
-This is typical operating behavior for a 3-terminal device or transistor.
-We can use an enhancement n-channel MOSFET to understand the IV characteristics and then directly apply them to p-channel and depletion-type devices.
Why do we scale?
1.)Improve Performance-More complex systems.
2.)Increase Transistor Density-Reduce cost per transistor & size of system.
3.)Reduce Power-Smaller transistors require less supply voltage.
Full Scaling (constant-Field)
-Reduce physical size of structures by 30% in the subsequent process.
-Reduce power supplies and thresholds by 30%
-We define: S ≡ Scaling Factor > 1
S = SQR(2)=1.4
What are some of the bottlenecks to design an IC?
-Complexity, no prior knowledge about real O/P.
-Need to have a method to dissipate heat.
-Supplying the power & routing across chip.
-Different types of noise; noise signal interruption.
-Reliability & robustness to errors, or defects, variations.
-Cost: CAD tools, design period, mask cost.
Constant-Voltage Scaling definition:
-Sometimes it is impractical to scale the voltages
-This can be due to:
1) existing I/O interface levels.
2) existing platform power supplies.
3) complexity of integrating multiple power supplies on chip.
-Constant-Voltage Scaling refers to scaling the physical quantities (W,L,tox,xj,NA) but leaving the voltages un-scaled (VT0, VGS, VDS)
-While this has some system advantages, it can lead to some unwanted increases in MOSFET characteristics.
-When we begin a design, we typically start with specification.
-We then size the transistors to achieve the desired performance.
-We saw how the sizes of the transistor effect the DC specs, specifically Vth.
-We also need to size the transistors so that for a given load capacitance, the gate can achieve a designed delay or rise/fall time.
-We can use the expressions for delay and rise/fall time that we derived to calculate the necessary transistor sizes.
-One of the components in the load capacitance is the interconnect.
-The interconnect refers to the poly-silicon and metal layers that are used to connect the gates together.
-As sizes on-chip shrink, we've seen that the scaling of interconnect is a big problem because the delay actually increases as you get smaller.
-In addition, the delay scales quadradically with length meaning that intra-module traces and global interconnect can create significant timing challenges.
-Modeling of the interconnect describes the equivalent circuits we use to describe the electrical behavior of the materials.
-The type of model we use is a trade-off between accuracy and simulation time
-We typically use 1 of the 3 following Typical use models:
1) Lumped Capacitance inter-module.
2) RC network intra-module and global.
3) Transmission Line global and off-chip.
The technique to estimate the overall delay between two nodes of an RC network tree.
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