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2200 Exam 1

Terms in this set (60)

How many different operations COULD this ISA have if it used all bits?
16 (2^4, think opcode)
Which instructions do these give us? Expressions, assignment statements
ADD, NAND, ADDI
Which instructions do these give us? High level data abstractions (variables)
SW, LW
Which instructions do these give us? Conditionals/loops
BEQ
What is a register file?
collection of registers that can be accessed by index
What is the ISA?
outlines the functions and instructions that the user should be able to use
All hardware components in the datapath share the same bus (T/F)
T
The program counter is a register (T/F), what does it do?
T, it is a register which stores the address of the next instruction
Which addressing mode is not supported by the LC-2200?
Base + index
Which type of logic is an AND gate?
Combinational
What is negative edge-triggered logic?
high to low and a falling edge
What does the IR hold?
Current instruction
What type of hardware component is used for main memory?
DRAM (Dynamic Random Access Memory)
What are the three macro states?
fetch, decode, execute
How many clock cycles are needed for SW?
4
What does sequential logic output rely on?
a Boolean combination of inputs AND the current state of the circuit (ex: state machine)
How do we write or read from/to a register? (think about data lines and enabling)
if writing, put the value on the Data In line (DIN)
if reading, data comes out the Data Out line (DOUT)
tell register if we're reading or writing using WrEn control line (WrEn = 1 means we want to write WrEN = 0 is for reading)
How many bits would it take to select and operation from an ALU using n bits?
log₂(n)
What is a tristate buffer?
it is the control signal that either allows the input to pass through or not (Think of it as a hardware switch/gate that connects or disconnects a wire)
What instruction(s) would we use the Sign Extender hardware for?
addi - immediate value to add
lw - offset of memory
sw - offset of memory
lea - PC + offset into memory
How is the state register and ROM similar to the MAR and RAM?
The MAR holds the address of the location in the RAM to access
The state register holds the state to be executing in the main ROM
What does fetch do/what happens each clock cycle?
(Grab instruction)
1. Drive value of PC, load into MAR
2. Drive memory, load IR
(Increment PC)
3. Drive PC, load A
4. Dunc = 11, drive ALU, load PC
What does decode do/what happens each clock cycle?
1. Extract the OPCODE from the IR and then pass that to sequencer ROM so that execute can run the right microcode
2. Use OPTest into MUX to select nextstate from sequencer ROM instead of main ROM
3. Sequencer ROM contains mapping from OPCODE -> start of EX for instruction in main ROM
What does execute do/what happens each clock cycle?
Execute microcode starting at the address coming out of the sequencer ROM
What is addressability?
Smallest space in memory that can be addressed (Your memory has addressability of 1 byte (8 bits) If you want to get a 4 bit value, you need to retrieve the full 8 bits because the addressability of the memory is 1 byte (8 bits))
What is an addressing mode?
refers to how operands are specified in an instruction
What is the LC-901 calling convention?
1.Saves temp registers on stack IF it needs values upon return (caller)
2.Places function parameters $a0-$a2 and saves ADDITIONAL ones on the stack (caller)
3.Allocates space for additional return values on the stack (caller)
4.Saves previous return address from current $ra on stack (caller)
5.Executes JALR $at, $ra (caller)
6.Saves previous FP then copies $sp into $fp (why FP is important) (callee)
7.Saves $s0-$s2 registers that it plans to use (callee)
8.Creates local variables which are allocated on the stack (callee)
9.Restores any saved register $s0 - $s3 (callee)
10.Stores return values as desired (callee)
11.Moves $sp to discard additional parameters (callee)
12.Restores any saved temp $t0 - $t3 registers from (caller)
The CPU consists of which two parts?
The control unit and the data path
Fetch macro state signals
1. PC -> MAR, PC -> A
Controls signals needed: DrPC, LdMAR, LdA
2. MEM[MAR] -> IR
Controls signals needed: DrMEM, LdIR
3. A + 1 -> PC
Controls signals needed: DrALU, LdPC
ADD instruction
1. add1: Ry -> A
Control signals: RegSel = 01, DrREG, LdA
2. add2: Rz -> B
Control Signals: RegSel = 10, DrREG, LdB
3. A=B -> Rx
Control Signals: func = 00, DrALU, RegSel = 00, WrREG
JALR
1. PC -> Ry
Control Signals: DrPC, RegSel = 01, WrREG
2. Rx -> PC
Control Signals: RegSel = 00, DrREG, LdPC
LW instruction
1. Ry - > A
Control Signals: RegSel = 01, DrREG, LdA
2. Sign-extended offset -> B
Control Signals: DrOFF, LdB
3. A + B -> MAR
Control Signals: func = 00, DrALU, LdMAR
4. MEM[MAR] -> Rx
Control Signals: DrMEM, RegSel = 00, WrREG
Interrupt (Async, external, Intentional, example: I/o device)
mechanism by which devices catch attention of the processor
Exception (Sync, Internal, overflow, examples: divide by zero, illegal memory)
programs may unintentionally perform certain illegal arguments (divide by zero) or follow execution path unintended in the program specification
Traps (Sync, Internal, Intentional: Yes and No, examples: system call, software interrupts, page fault).
(Programs often make system calls to read/write files or for other such services from the system that require special handling. ) Traps allow the program to fall into the operating system, which will decide what the program wants.
Interrupt vector table
A table of pointers in the operating system, indexed by the type of interrupt, with each entry pointing to the first instruction of a handler procedure for that interrupt
How does the processor know there is an interrupt?
We can add a hardware line on the datapath bus of the processor. At the end of each instruction execution, the processor samples this line to see if there is an interrupt pending.
When does an interrupt happen in relation to an instruction execution?
the interrupt will be taken only after the instruction execution is complete
How are cascading interrupts handled?
1. A new instruction is created to turn off interrupts: disable interrupts
2. A new instruction to turn on interrupts: enable interrupts
Handler Code
Save PC value to return later -> save $k0
Continues user's code, before interrupt occurred -> enable interrupts
Save registers that the handler could overwrite -> save processor registers
Execute code associated with ICT address -> execute device code
Put values back in registers to restore "state" -> restore processor registers
Prevent interrupts, to ensure atomicity in fetch -> disable interrupts
Put PC back into $k0 to know where to return to -> restore $k0
Continues user's code, before interrupt occurred -> return to original program
What does Enable Interrupts (EI) command do?
allow interrupts to be handled (interrupts on)
What does Disable Interrupts (DI) do?
prevents interrupts from being handled (interrupts off)
What does Return from Interrupt (RETI) do?
it's an atomic instruction to Enable interrupts and sets the PC equal to the value in $k0 (executes EI and JALR)
Why do we need the user and system stacks?
To ensure that the system stack when saving processor registers is not overwriting any info in the program's stack
What performs stack switching?
FSM
What is privileged mode?
the mode bit in processor which denotes user or kernel and is set in the INT macro state
it tells the hardware which $sp register to use
Space metric
how much memory a program (not process) uses
T/F: The smaller the space metric, the smaller the time metric?
F (not all lines of a program are executed, can have a large program with a lot of branches)
time metric
how long a program takes to run (determined by # of instructions, # of clock cycles each instruction takes and the clock cycle time)
Static instruction frequency
number of times instruction occurs in code
Dynamic instruction frequency
number of times an instruction is executed when a program is run
arithmetic mean
average of all individual program executions
Pro and con of arithmetic mean
good to determine how multiple programs take to run but can be biased
Weighted Arithmetic Mean
Weighted average of the execution times
Geometric mean
path root of the product of the p values
harmonic mean
arithmetic mean of the reciprocal of the values and then the reciprocal of this value
memory footprint
total space occupied by the program in memory
speedup
compares the execution times either on two processors or before/after improvement
improvement in execution time
(old exec time-new exec time) /old exec time
Throughput
number of instructions executed by the processor per unit of time
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