set of software functions that facilitate the use of an I/O port
Product development cycle:
Analyze the problem, High level design, Engineering design, Implementation, and Testing
begin with solutions and build up to a problem statement
measure of how fast the program executes
number of memory bits required
Control Unit (CU)
orchestrates the sequence of operations in teh processor.
Instruction Register (IR)
contains the opcode for the current instruction
Arithemetic logic unit (ALU)
performs aritemetic operations such as addition, subtraction, multiplication and division. Also performs logical operations such as and, or and shift.
Program counter (PC)
points to the memory containing the instruction to execute next
Bus interface unit (BIU)
reads data from the bus during a read cycle and writes data onto bus during a write cycle
Effective address register (EAR)
contains the data address for the current instruction
Inherent addressing mode
Instructions operate completely within the processor and require no memory data fetches
Immediate addressing mode
Data is found in the instruction itself
Direct / Extended addressing mode
Instruction uses the absolute address to specify the memory data location
Indexed addressing mode
uses a register pointer to access data in memory
PC-relative addressing mode
used to encode branch instruction
biggest 8bit unsigned number
Negative bit (N)
set if the result is negative ( MSB is 1 )
Zero bit (Z)
set if the result is zero
Overflow bit (V)
set if SIGNED overflow
Carry bit (C)
set if UNSIGNED overflow
Execution of a Moore FSM repeats this:
Perform output (based on current state), wait a prescribed amount of time, input and then go to next state(depends on input and current state)
Execution of a Mealy FSM repeats this:
Wait prescribed amount of time, input, perform output (based on input and current state), go to next state (depends on input and current state)
What register has three bits that control TCNT?
What sets the TOF flag in the TFLG2 register?
When the TCNT register overflows from $FFFF to 0
What must be done in order to use TCNT?
bit 7 of the TSCR1register must be set
time between when the I/O devices needs service and the time when the service is initiated
maximum bytes per second that can be processed by the system
Blind cycle waiting
method where the software simply waits a fixed amount of time and assumes the I/O will complete before that fixed delay has elapsed
When should Blind cycle be used?
When the I/O speed is short and predictable
software loop that checks the I/O status waiting for the done state
When should Busy waiting be used?
situations where the software system is relatively simple and real time response is not important
The automatic transfer of software execution in response to a hardware event that is asynchronous with the current software execution
uses a clock interrupt to periodically check the I/O status
Interrupt Enable bit (I)
Inerrupts are enabled by setting I = 0. Interrupts are disabled by setting I=1 ( TIOS)
Which registers are saved during an interrupt request?
X, B, A, Y, PC and CCR
what type of variables must be used for parameter passing between threads?
Shared global memory variables
When is busy-waiting synchronization appropriate>
when the I/O timing is predictable, and when the I/O structure is simple and fixed. Best when there is nothing else that needs to be happening
When is Interrupt synchronization appropriate?
when I/O timing is variable and the structure is complex.
When are periodic interrupts appropriate?
For real-time clocks, data acquisition, and control systems.
What is an atomic operation?
sequence that once started will always finish, and can not be interrupted.
How is an atomic operation implemented?
1) save the current value of CR, 2) disable interrupts, 3) execute the operation, and 4) restore the CCR
What are the steps that occur when an interrupt is processed?
1) Finish current instruction, 2) Push registers on the stack, 3) get interrupt vector, 4) execute the ISR, 5) execute the rti instruction
to Arm means
to enable interrupts by setting bit of TIE
Sequence of interrupt events:
1) hardware needs service (busy to done transition), 2) setting of a trigger flag, 3) Thread-switch, 4) execution of ISR, and 5) return control by using rti
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