Consider the folded-cascode op amp of Fig.earlier when loaded with a $10-\mathrm{pF}$ capacitance. What should the bias current $I$ be to obtain a slew rate of at least 10 $\mathrm{V} / \mu \mathrm{s}$ ? If the input-stage transistors are operated at overdrive voltages of $0.2 \mathrm{~V}$, what is the unity-gain bandwidth realized? If the two nondominant poles have the same frequency of $25 \mathrm{MHz}$, what is the phase margin obtained? If it is required to have a phase margin of $75^{\circ}$, what must $f_t$ be reduced to? By what amount should $C_L$ be increased? What is the new value of $S R$ ?

For the circuit in Fig. find in terms of $i_\epsilon$ : (a) the signal voltage at the base of $Q_6$; (b) the signal current in the emitter of $Q_7$; (c) the signal current in the base of $Q_7 ;$ (d) the signal voltage at the base of $Q_7 ;$ (e) the input resistance seen by the left-hand-side signal current source $\alpha a_e$, (Note: For simplicity, assume that $I_{C \subset} \simeq I_{\mathrm{C}}=I_{C \sigma}$ )

If in the circuit of Fig. the $Q_{18}-Q_{19}$ network is replaced by two diode-connected transistors, find the current in $Q_{14}$ and $Q_{20}$ (Hint: Use the result of Exercise

For the folded-cascode op amp in Fig. 12.9 utilizing power supplies of $\pm 1 \mathrm{~V}$, find the values of $V_{\text {HLIS1 }}, V_{\text {BLLSS }}$, and $V_{\text {BIAss }}$ to maximize the allowable range of $V_{B C S}$ and $v_{o r}$ Assume that all transistors are operated at equal overdrive voltages of $0.15 \mathrm{~V}$. Assume $\left|V_t\right|$ for all devices is $0.45 \mathrm{~V}$. Specify the maximum range of $V_{I C M}$ and of $v_\sigma$.

Neglect the voltage drops across $R_{1}$ and $R_{2}$ and assume that $V_{C C}=V_{E E}=15 \mathrm{V}.$ Show that the input common-mode range of the 741 is approximately –12.9 V to+14.7 V. (Assume that $V_{B E} \simeq 0.6 \mathrm{V}$ and that to avoid saturation $V_{C B} \geq-0.3 \mathrm{V}$ for an npn transistor, and $V_{B C} \geq-0.3 \mathrm{V}$ for a pnp transistor.)

If the circuit of Fig. earlier utilizes $\pm 1.65-V$ power supplies and the power dissipation is to be limited to $1 \mathrm{~mW}$, find the values of $I_B$ and $I$. To avoid turning off the current mirror during slewing, select $I_B$ to be $20 \%$ larger than $I$.

Design the Widlar current source of Fig. to generate a current $I_{C l 0}=10 \mu \mathrm{A}$ given that $I_{\mathrm{REF}}=$ $1 \mathrm{~mA}$. If at a collector current of $1 \mathrm{~mA}, V_{B E}=0.7 \mathrm{~V}$, find $V_{B E 11}$ and $V_{\text {GEE }}$

a) Show that the PSRR ${ }^{-}$of a CMOS two-stage op amp for which all transistors have the same channel length and are operated at equal $\left|V_{O V}\right|$ is given by

$$\mathrm{PSRR}^{-}=2\left|\frac{V_A}{V_{O V}}\right|^2$$

(b) For $\left|V_{o n}\right|=0.2 \mathrm{~V}$, what is the minimum channel length required to obtain a PSRR ${ }^{-}$of $80 \mathrm{~dB}$ ? For the technology available, $\left|V_\lambda^{\prime}\right|=20 \mathrm{~V} / \mu \mathrm{m}$.

For the circuit in Fig., neglect base currents and use the exponential $i_C-v_{M E}$ relationship to show that

$$I_3=I_1 \sqrt{\frac{I_{S 3} I_{S 4}}{I_{S 1} I_{S 2}}}$$

Sketch the circuit of a two-stage CMOS amplifier having the structure of Fig. but utilizing NMOS transistors in the input stage (i.e., $Q_1$ and $Q_2$ ).

For the standard $n p n$ transistor whose parameters are given in Section earlier find approximate values for the following parameters at $I_C=1 \mathrm{~mA}: V_{R E}, g_m, r_c, r_\pi$, and $r_o$.

A two-stage CMOS op amp resembling that in Fig. earlier is found to have a slew rate of $60 \mathrm{~V} / \mu \mathrm{s}$ and a unity-gain bandwidth $f_t$ of $50 \mathrm{MHz}$ (a) Estimate the value of the overdrive voltage at which the input-stage transistors are operating. (b) If the first-stage bias current $I=100 \mu \mathrm{A}$, what value of $C_C$ must be used? (c) For a process for which $\mu_\rho C_{\alpha x}=50 \mu \mathrm{A} / \mathrm{V}^2$, what $W / L$ ratio applies for $Q_1$ and $Q_2$ ?

A particular design of the two-stage CMOS operational amplifier of Fig. utilizes $\pm 1-\mathrm{V}$ power supplies. All transistors are operated at overdrive voltages of $0.15-\mathrm{V}$ magnitude. The process technology provides devices with $V_{t n}=\left|V_{t p}\right|=0.45 \mathrm{~V}$. Find the input common-mode range and the range allowed for $v_o$

A particular design of the two-stage CMOS operational amplifier of Fig. utilizes $\pm 1-\mathrm{V}$ power supplies. All transistors are operated at overdrive voltages of $0.15-\mathrm{V}$ magnitude. The process technology provides devices with $V_{t n}=\left|V_{t p}\right|=0.45 \mathrm{~V}$. Find the input common-mode range and the range allowed for $v_o$