Show how to make the 8-to-3 priority encoder of Figure 9-20 using two 4-to-2 priority encoders and any additional necessary gates.

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A $8$ to $3$ Priority encoder is to be realized using two $4$ to $2$ priority encoders. \ \
The $8$ inputs are divided into two groups of $4$, first $4:2$ encoder has $Y_0,Y_1,Y_2$ and $Y_3$ inputs and second encoder has $Y_4,Y_5,Y_6$ and $Y_7$ inputs.\ \
Since, both the encoders are already priority encoder, we have to design circuit such that if higher priority inputs i.e from $Y_4$ to $Y_7$ are active then the first encoder becomes inactive.\ \
Let $a,b$ be the output of first encoder and $E_1$ is the signal that distinguishes all $0$ case from $Y_0$ it also indicates that encoder is active.\ \
Similarly let $c,d$ and $E_2$ be the signals from second encoder.\ \
The MSB for $8:3$ encoder is $ E_2$ and $E_3 = E_1 + E_2$ is the distinguishing signal.
$$ p = E_2$$
If second encoder is active, then the output from first encoder should not contribute in output, therefore the outputs from first encoder is passed through AND gates with the inverted $E_2$, and the total output is given by OR of these signals and $c,d$.
\begin{align*}
q &= c + a \cdot (E_2)' \
r &= d + b \cdot (E_2)'
\end{align*}
The resultant table for $8:3$ priority encoder is 
$$
\begin{tabular}{llllrrrr|lrrr|r}
$Y_0$                      & $Y_1$                      & $Y_2$                      & $Y_3$                      & $Y_4$  & $Y_5$  & $Y_6$  & $Y_7$ &  & \multicolumn{1}{l}{p} & \multicolumn{1}{l}{q} & \multicolumn{1}{l|}{r} & $E_3$ \ 
\hline
\multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & 0                     & 0                     & 0                     & 0                      &  & 0                     & 0                     & 0                      & 0                      \
\multicolumn{1}{r}{1} & \multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & 0                     & 0                     & 0                     & 0                      &  & 0                     & 0                     & 0                      & 1                      \
x                     & \multicolumn{1}{r}{1} & \multicolumn{1}{r}{0} & \multicolumn{1}{r}{0} & 0                     & 0                     & 0                     & 0                      &  & 0                     & 0                     & 1                      & 1                      \
x                     & x                     & \multicolumn{1}{r}{1} & \multicolumn{1}{r}{0} & 0                     & 0                     & 0                     & 0                      &  & 0                     & 1                     & 0                      & 1                      \
x                     & x                     & x                     & \multicolumn{1}{r}{1} & 0                     & 0                     & 0                     & 0                      &  & 0                     & 1                     & 1                      & 1                      \
x                     & x                     & x                     & x                     & 1                     & 0                     & 0                     & 0                      &  & 1                     & 0                     & 0                      & 1                      \
x                     & x                     & x                     & x                     & \multicolumn{1}{l}{x} & 1                     & 0                     & 0                      &  & 1                     & 0                     & 1                      & 1                      \
x                     & x                     & x                     & x                     & \multicolumn{1}{l}{x} & \multicolumn{1}{l}{x} & 1                     & 0                      &  & 1                     & 1                     & 0                      & 1                      \
x                     & x                     & x                     & x                     & \multicolumn{1}{l}{x} & \multicolumn{1}{l}{x} & \multicolumn{1}{l}{x} & 1                      &  & 1                     & 1                     & 1                      & 1                     
\end{tabular}
$$

The circuit implementation is shown in the diagram below:

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Show how to make the 8-to-3 priority encoder of Figure 9-20 using two 4-to-2 priority encoders and any additional necessary gates.

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