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Question

Suppose that two numbers in signed two’s-complement form have been added. S1S_1 is the sign bit of the first number, S2S_2 is the sign bit of the second number, and STS_T is the sign bit of the total. Suppose that we want a logic circuit with output E that is high if either overflow or underflow has occurred; otherwise, E is to remain low. 1. Write the truth table. 2. Find an SOP expression composed of minterms for E. 3. Draw a circuit that yields E, using AND, OR, and NOT gates.

Solution

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We know from the previous that overflow and underflow are not possible if the two numbers to be added have opposite signs. Underflow or overflow occurr when the two numbers to be added have the same sign and the result has the opposite sign.

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