Using JK flip-flops, (a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6. (b) Draw the logic diagram of the counter.

Show that a BCD ripple counter can be constructed using a four-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010.

A sequential circuit has two D flip- flops, one input X, and one output Y. The logic diagram of the circuit is shown. Derive the state table and state diagram of the circuit.

A sequential circuit has one flip-flop Q, two inputs X and Y, and one output S. The circuit consists of a D flip-flop with S as its output and logic implementing the function

$$D=X \oplus Y \oplus S$$

with D as the input to the D flip-flop. Derive the state table and state diagram of the sequential circuit.

What is the function of the program counter register? Of the condition-code register?

A two-stage counter has two input control lines, M and N. The count sequences are as follows:

$$\begin{array}{ll} M N & {\text { Sequence }} \\ \hline 00 & 0,1,2,3,0, \ldots . \\ 01 & 0,1,0,1,0,1, \ldots \\ 10 & 2,0,2,0,2,0, \ldots \\ 11 & 1,2,1,2,1,2, \ldots \end{array}$$

(a) Design the counter assuming the outputs come directly from J-K flip-flops. (b) Design the counter assuming a two-stage binary counter is used with the J-K flip-flop outputs decoded.

Design a modulus-1000 counter by using decade counters.

Let V = (000, 001, 010, .... 110, 111). For each four-bit sequence b1b2b3b4 draw an edge from the element b1b2b3 to the element b2b3b4 in V.(a) Draw the graph G = (V, E) as described, (b) Find a directed Euler circuit for G. (c) Equally space eight 0’s and eight 1 ’s around the edge of a rotating (clockwise) drum so that these 16 bits form a circular sequence where the (consecutive) subsequences of length 4 provide the binary representations of 0, 1, 2, ..., 14, 15 in some order.

What is the function of the program counter register? Of the MCU?

Design a four-bit binary synchronous counter with D flip-flops.

A modulo 8 counter cycles through the states $Q_{0} Q_{1} Q_{2} Q_{3}=1000$, 1100, 0100, 0110, 0010, 0011, 0001, 1001. The counter has eight outputs: $Z_{0}=1$ when the counter is in state 1000 and the CLK is 0 and $Z_{0}=0$ otherwise; $Z_{1}=1$ when the counter is in state 1100 and the CLK is 0 and $Z_{1}=0$ otherwise,...: $Z_{7}=1$ when the counter is in state 1001 and the CLK is 0 and $Z_{7}=0$ otherwise. The counter has an asynchronous active-low reset input ClrN. (a) Derive minimum equations for the counter outputs. (b) Assume the counter is implemented using D flip-flops. Find minimum input equations for the flip-flops. (c) Assume the counter is implemented using D-CE flip-flops. Find minimum input equations for the flip-flops. (d) Write a VHDL behavioral description of the counter. Assume the flip-flops are positive edge triggered. (e) Write a VHDL dataflow description of the counter using the equations from part (b). Simulate the counter for a cycle to verify your code. (f ) Write a VHDL dataflow description of the counter using the equations from part (c). Simulate the counter for a cycle to verify your code.

a) Determine the value of the integer variable counter after execution of the following program segment. (Here i, j, and k are integer variables.) counter : = 0 for i := 1 to 12 docounter := counter + 1for j : = 5 to 10 docounter := counter + 2for k := 15 down to 8 docounter := counter + 3 b) Which counting principle is at play in part (a)?

A Gray code is a sequence of binary numbers with the property that no more than 1 bit changes in going from one element of the sequence to another. For example, here is a 3-bit binary Gray code: 000, 001, 011, 010, 110, 111, 101, and 100. Using three D flip-flops and a PLA, construct a 3-bit Gray code counter that has two inputs: reset, which sets the counter to 000, and inc, which makes the counter go to the next value in the sequence. Note that the code is cyclic, so that the value after 100 in the sequence is 000.

Construct a 3-bit counter using three D flip-flops and a selection of gates. The inputs should consist of a signal that resets the counter to 0, called reset, and a signal to increment the counter, called inc. The outputs should be the value of the counter. When the counter has value 7 and is incremented, it should wrap around and become 0.