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Question

# Write the VHDL code for an S-R flip-flop with a rising-edge clock. Use standard logic, and output 'X' if S = R = '1' at a rising clock edge.

Solution

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We need to write the VHDL code for an S-R flip-flop. The active edge of the flip-flop is the rising edge.

The operation of a $\textbf{S-R flip-flop}$ is similar to the operation of an S-R latch except that any changes in the state occur right after the active edge of the clock input.

$\bullet$ $S=R=1$ is a $\textit{disallowed state}$ and the output $Q$ should then be set to $X$.

$\bullet$ $Q$ is set to 1 after the active clock edge if $S=1$ and $R=0$.

$\bullet$ $Q$ is reset to 0 after the active clock edge if $S=0$ and $R=1$.

$\bullet$ No state changes occur if $S=R=0$.

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