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Question

Write the VHDL code for an S-R flip-flop with a rising-edge clock. Use standard logic, and output 'X' if S = R = '1' at a rising clock edge.

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We need to write the VHDL code for an S-R flip-flop. The active edge of the flip-flop is the rising edge.

The operation of a S-R flip-flop\textbf{S-R flip-flop} is similar to the operation of an S-R latch except that any changes in the state occur right after the active edge of the clock input.

\bullet S=R=1S=R=1 is a disallowed state\textit{disallowed state} and the output QQ should then be set to XX.

\bullet QQ is set to 1 after the active clock edge if S=1S=1 and R=0R=0.

\bullet QQ is reset to 0 after the active clock edge if S=0S=0 and R=1R=1.

\bullet No state changes occur if S=R=0S=R=0.

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