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DECA 2 Mentimeter 2 - EEP0 and EEP1
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Terms in this set (24)
ADD R1,R2
A. Adds R1 to R2
B. Adds R2 to R1
C. Adds 1 to R2
D. Adds 2 to R1
B. Adds R2 to R1
ADD R0,#-1
A. Is not possible
B. Is possible and the same as ADD R0,#255
C. Does not make sense because EEP0 is unsigned
B. Is possible and the same as ADD R0,#255
JMP #10
A. Jumps to machine code #0010
B. Jumps to address #10 in RAM
C. Jumps to address #10 in ROMD
D. Jumps to the address given by mem[10]
C. Jumps to address #10 in ROMD
JNE #100 jumps if
A. The last result was not zero
B. Z = 0
C. Z = 1
D. The most recent SUB, ADD, ADC instruction had ALU.OUT = 0.
A. The last result was not zero
After MOV R1,#10; ADD R1, #10; SBC R1, #10
A. R1 = 0
B. R1 = 9
C. R1 = 10
D. R1 = 11
B. R1 = 9
If initially R2=y, after ADD R2,R2; ADD R2, R2; ADD R2, R2
A. R2 = 3y mod 256
B. R2 = 6y mod 256
C. R2 = 8y mod 256
D. ADD R2, R2 is not allowed in EEP0.
C. R2 = 8y mod 256
Which can be implemented in a EEP1 MOV instruction?
R0 := 1
R0 := -1
R0 := R1
R0 := -R1
R0 := R1 + 1
R0 := R1 - 1
R0 := R1 + 16
R0 := 1 YES
R0 := -1 YES
R0 := R1 YES
R0 := -R1 NO
R0 := R1 + 1 YES
R0 := R1 - 1 YES
R0 := R1 + 16 NO
What can be implemented in one EEP1 ADD instruction?
A. R0 := R0+ 10
B. R0 := R0- 40
C. R0 := 2 *R0
D. R0 :=2*R0 - 1
E. R0 := R0+ R1 - 2
F. R0 := R0+ 2 - R1
A. R0 := R0+ 10
B. R0 := R0- 40
C. R0 := 2 *R0
D. R0 :=2*R0 - 1
E. R0 := R0+ R1 - 2
F. You can't have negative registers
EEP1: SBC R0, R1, #1 implements:
A. R0 := R0 - R1
B. R0 := R0 - R1 + C -2
C. R0 := R0 - R1 + C -1
D. R0 := R0 - R1 + C
E. R0 := R0 - R1 - C + 1
C. R0 := R0 - R1 + C -1
The maximum size of an EEP0 program is
A. 16 instructions
B. 17 instructions
C. 64 instructions
D. 256 instructions
E. 512 instructions
D. 256 instructions
An EEP0 program terminates when it hits a jump to self. The max number of cycles before termination in a program that does terminate is:
A. 255
B. 2^256
C. > 2^(8*256)
C. > 2^(8*256)
Register is to char as RAM is to
A. char[]
B. char [][]
C. int []
D. const char[]
A. char[]
EEP0 registers work like an array of 4 8 bit numbers in C++
A. Yes
B. No, the index can't be varied.
C. No, they are neither signed nor unsigned.
B. No, the index can't be varied.
SUB R0,R0
A. Is not allowed.
B. Sets R0 to 0.
C. Does not change R0.
B. Sets R0 to 0.
R2 initially contains 0x80. After SUB R2, #1
A. V = 0, C = 0
B. V = 0, C = 1
C. V = 1, C = 0
D. V = 1, C = 1
E. Depends whether R2 was -128 or +128.
D. V = 1, C = 1
ADC would normally be used in a multi-word addition.
A. As the first instruction.
B. As all of the instructions.
C. As all but the first instruction.
C. As all but the first instruction.
C = overflow?
A. No, C is carry, not overflow.
B. In some cases, C is overflow.
C. Only if the last instruction was an ADD.
D. Yes, C is always overflow.
B. In some cases, C is overflow.
Carry or overflow.
CV are written
A. Whenever NZ are written.
B. Less often than NZ are written.
C. More often than NZ are written.
B. Less often than NZ are written.
C is reset to 0
A. Never.
B. After JCS.
C. After an ADD, SUB, ADC instruction without Carry.
D. After JCS or an ADD, SUB, ADC instruction without Carry.
C. After an ADD, SUB, ADC instruction without Carry.
SUB is implemented in hardware
A. By inverting bits and using a +1 block.
B. By inverting bits and using ALU Cin = 1
C. By inverting bits and ALU Cin = 0 if the number is signed.
B. By inverting bits and using ALU Cin = 1
SUB makes sense with unsigned numbers
A. Yes
B. No
A. Yes
EEP0 Flags
A. N is signedOverflow, V is unsigned Overflow.
B. C is unsigned Overflow, V is signed Overflow.
C. C is signed Overflow V is signed Overflow.
D. C is Carryout, V is signed Overflow.
E. C is CarryOut, C is unsigned Overflow.
B. C is unsigned Overflow, V is signed Overflow.
D. C is Carryout, V is signed Overflow.
E. C is CarryOut, C is unsigned Overflow.
The X bits in EEP0 instructions
Are conventionally set to 0.
EEP0 is...
A. Harvard Architecture.
B. Von Neumann Architecture.
C. Fixed Program Variable Data.
A. Harvard Architecture.
C. Fixed Program Variable Data.
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