Terms in this set (61)
1.Power dissipation in CMOS
Static CMOS gates are very power efficient and they dissipate nearly zero power while idle.
Power dissipation in CMOS is of 2 types namely
1.Static power dissipation
2.Dynamic power dissipation
Static power dissipation occurs due to
1.Sub threshold condition through OFF transistors
2.Tunneling current through gate oxide
3.Leakage through reverse biased diodes
4.Contention current through ratioed circuits
Dynamic power dissipation occurs due to
1.Charging and discharging of load capacitance
2.Short circuit current while both pMOS and nMOS networks are partially ON
Scaling improves the figure of merit by shrinking the dimensions of transistors and interconnections between them.
There are 2 types of scaling
Transistor scaling further classified into
a.Constant field scaling
Need for testing
Manufacturing process of an IC or chip is a complex process.Due to dust particles and small imperfections in material and photomasking,the chip may not work properly.This results in fault.So it is necessary to test the chip for its performance and functionality before reaching the customer
Logic verification principles
1.Test benches and harnesses
Lambda layout rules
1.Allow first order scaling by linearizing the resolution of the complete wafer implementation.
2.To move a design from 4 micron to 2 micron, simply reduce the value of lambda.
3.Worked well for 4 micron processes down to 1.2 micron processes.
4.However, in general, processes rarely shrink uniformly.
5.Probably not sufficient for submicron processes.
What is design margin
The additional performance capability above required standard basic system parameters that may be specified by a system designer to compensate for uncertainties.
What is device modelling
Before a circuit is designed, to be integrated by CMOS VLSI technology, a model must be adopted which will describe behavior of all components successfully. A model means a set of mathematical formulas, circuit representations, tables, reference standards etc
Synchronizers accept an input that can change at arbitrary times and produce an output aligned to the synchronizers clock.This has a non zero probability of producing a metastable output
Types of testing
1.Functionality test or logic verification
2.Silicon debug test
What is logic verification
Functionality test is also called logic verification.They are the first tests that are performed during the design process.The test proves that the circuit is functionally equivalent to some specification
Verilog HDL supports basic logic gates as predefined primitives.Primitives are instantiated like modules.These are predefined in Verilog HDL.All logic circuits can be designed using basic gates.There are 3 types of gate primitives
1.Multiple input gates
2.Multiple output gates
Non ideal IV effects
1.Velocity saturation & mobile degradation
2.Channel length modulation
4.Sub threshold condition
Procedural assignments update the value of reg,integer,real or time variables.The value placed on a variable will remain unchanged until another procedural assignment updates the variable with a different value.There are 2 types of procedural assignments
2.Non blocking assignments
Switch level modelling
This modelling has the lowest level of abstraction.In this,the designers design the leaf-level models using transistors.In verilog HDL,transistors are also called switches.The design is very complex in this modelling.Few hardware designers work at switch level modelling.
Why is tunneling current higher for nMOS transistors than pMOS with silica gate?
Because the electrons tunnel from conduction band while the holes tunnel from valence band
Objective of layout rules
To build reliable functional circuits with small are.The rules represent a compromise between performance and yield.The rules also represent tolerance that ensures very high probability of correct fabrication and subsequent operation
State the reason for speed advantage of CVSL family
CVSL has a potential speed advantage because all the logistics are performed using nMOS transistors.This will reduce the input capacitance.
Qualities of ideal sequencing method
1.Introduce no sequencing overhead
2.allow sequencing elements back to back with no logic in between
3.Grant the designer flexibility in balancing the amount of logic in each clock cycle.
4.Tolerate moderate amounts of clock skew without degrading performance.
5.Consume zero area and power
Why does interconnect increase the circuit delay?
1.Wire capacitance adds loading to each gate.
2.Long wires with significant resistance contribute distributed RC delay or flight time
Advantages of differential flip flops
1.Accept inputs and produce true outputs in true and complementary form
2.Circuits are built from clocked sense amplifiers to respond with small differential input voltages
Delay specifications available in verilog HDL for modelling a logic gate
1.Rise time delay
2.Fall time delay
3.Turn off time delay
Influence of voltage scaling on power and delay
Voltage scaling on power is expressed by a factor of 1/S and that of power is unity
Design guidelines for IDDQ testing
IDDQ is used for testing the bridging faults.When complementary CMOS logic gate is not switching,the circuit draws no DC current except leakage current.When a bridging fault occurs,then for some combination of input conditions,a measurable DC Idd will flow. IDDQ testing is stopped when sub threshold leakage current increases
What is transport delay model?
Transport delay model represents the propagation delay of signals from the module input to its outputs in Verilog
In VHDL,different subprograms can be defined with the same name.But based on their signature,the compiler will determine which subprogram is called based on context
Body effect refers to the change in the transistor threshold voltage (VT) resulting from a voltage difference between the transistor source and body.Because the voltage difference between the source and body affects the VT, the body can be thought of as a second gate that helps determine how the transistor turns on and off.
What is RTL modelling in Verilog?
RTL is an acronym for register transfer level. This implies that your Verilog code describes how data is transformed as it is passed from register to register. The transforming of the data is performed by the combinational logic that exists between the registers.
Operators used in Verilog HDL
5.Concatenation and replication operators
Pull down device
A pull-down device when energized will pull the output to ground. In MOS technology, NMOS is always used as pull-down device since it can provide a GOOD "0" i.e. (LOW ).
What is epitaxy?
the natural or artificial growth of crystals on a crystalline substrate that determines their orientation
Twin tub process
It is also possible to create both a p-well and an n-well for the n-MOSFET's and p-MOSFET respectively in the twin well or twin tub technology. Such a choice means that the process is independent of the dopant type of the starting substrate (provided it is only lightly doped).
What is AOI?
The AND-OR-Invert (AOI) gate is a two-level complex logic cell constructed from one or more AND gates followed by a NOR gate. The AOI gate is a complement of the OR-AND-Invert Gate.
Define fabrication process
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices.
FSM stands for Finite state Machine.A machine consisting of a set of states, a start state, an input, and a transition function that maps input and current states to a next state. Machine begins in the start state with an input. It changes to new states depending on the transition function. The transition function depends on current states and inputs. The output of the machine depends on input and/or current state.
There are two types of FSMs which are popularly used in the digital design. They are
Define mealy machine
A Mealy machine is a deterministic finite-state transducer: for each state and input, at most one transition is possible.
Define AOI logic function
AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of one or more AND gates followed by a NOR gate. ... The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND gate.
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output.
After completion of the design block,it is tested by applying stimulus and then checking the results.This block is called stimulus block.It is also called a test bench
A field-programmable gate array (FPGA) is an integrated circuit (IC) that can be programmed in the field after manufacture. FPGAs are similar in principle to, but have vastly wider potential application than, programmable read-only memory (PROM) chips.
Channel length modulation
The current between drain and source terminals is constant and independent of the applied
voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junctionto grow, reducing the length of the effective channel.
Latch up is a condition in which the parasitic components give rise to the establishment of low
resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem
Structural gate level modeling
Structural modeling describes the digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are
In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. It uses a combination of behavioral and dataflow constructs. Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived.
A transition or event on one of multiple signals or events can be used to trigger execution of a statement or a block of statements. For example, in the procedural statement always @ (a,b,c), the block of statements that follows the always statement is executed whenever there is a transition on signals a or b or c.
Synthesis is the process of deriving a list of components and their interconnections (netlist) from the digital system model described by HDL.
The statements in a sequential bock are executed in the order they are specified. The keywords used to enclose the statements in the block are begin and end.
Identifiers are names given to objects so that they can be referenced in a design. They are made up of alphanumeric characters, underscore or $ sign. the first letter should be an alphabet or underscore. They are case sensitive.
Strong vertical electric fields resulting from large Vgs cause the carriers to scatter against the surface and also reduce the carrier mobility μ. This effect is called mobility degradation. It can be modeled by replacing μ with a smaller μeff.
When is the channel of MOSFET is said to be pinched off?
If Vds becomes sufficiently large that Vgd < Vt, the channel is no longer inverted near the drain and becomes pinched off.
Noise margin is closely related to the DC voltage characteristics. This parameter allows you to determine the allowable noise voltage on the input of a gate so that the output will not be corrupted. The specification most commonly used to describe noise margin (or noise immunity) uses two parameters: the LOW noise margin, NML, and the HIGH noise margin, NMH.
2 interconnect processes
(i) Copper damascene process
(ii) Low k dielectrics
CMOS process enhancement for transistors
(i) Multiple threshold voltages and oxide thickness
(ii) Silicon on insulator
Both npn and pnp bipolar transistors can be added to a CMOS process, which is then called a BiCMOS process. These processes tend to be used for specialized analog or high-voltage circuits.
Role of stick diagram in MOS circuit design process
Stick diagrams are used to convey layout information through the use of color coded rectangles representing components and interconnections.
Role of layouts in MOS circuit design process
Layout helps us to understand how the circuit is built physically. As layout is time-consuming, it is important to have fast ways to plan layout and estimate area before committing to a full layout.
Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current
The path in a logic circuit with the longest delay from input to output is called critical path. The delay on this path decides the maximum frequency of operation of the circuit.
Ratioed circuits use weak pull-up devices and stronger pulldown devices. They reduce the input capacitance and hence improve logical effort by eliminating large pMOS transistors loading the inputs, but depend on the correct ratio of
pull-up to pull-down strength. Ratioed circuits also dissipate static power while the output is low.
In some cases, one input transition may be more important than the other. Hl-skew gates favor the rising output transition and LO-skew gates favor the falling output transition. This favoring can be done by decreasing the size of the noncritical transistor.